Circuit designers use electronic design automation (EDA) tools, a category of computer aided design (CAD) tools, to create a functional circuit design, including a register transfer level (RTL) representation of the functional circuit design, synthesize a “netlist” from the RTL representation, and implement a layout from the netlists. Synthesis of the netlist and implementation of the layout involve simulating the operation of the circuit and determining where cells should be placed and where interconnects that couple the cells together should be routed. EDA tools allow designers to construct a circuit, simulate its performance, estimate its power consumption and area and predict its yield using a computer and without requiring the costly and lengthy process of fabrication.
The design of a circuit has two major stages: functional design and structural framework. The functional design of a circuit, such as an Application Specific Integrated Circuit (ASIC), is typically performed by a design team that provides the specification, architecture, RTL and design verification. The structural framework of the circuit design is typically performed by a design implementation team that oversees logic connectivity, partitioning and floorplanning of the circuit design. Additionally, the structural framework of a circuit design is analyzed and corrected during the design process to ensure that the design withstands all of the desired physical implementations aspects until the final design stage. The quality of a circuit design netlist is typically analyzed based on different structural rules to identify design problems with respect to physical implementation and before being sent to the physical implementation team.
A structural analysis tool, a type of EDA tool, is often used to analyze a netlist before the handoff to the physical implementation team. Structural analysis tools, such as a netlist audit tool, can be used to identify physical implementation design problems. These netlist audit tools, however, require new tool setup and generate large reports and logs that are difficult to analyze and cumbersome to filter the waivers and noncritical violations according to design constraints (e.g., timing constraints). Due to the volume of generated reports, real violations can be masked due to the sheer size of the reports. As such, design teams can have difficulty in identifying real issues because of the size of reports that included waivable, noncritical violations also. Additionally, creating a new tool setup to analyze the design typically requires different file formats to be created and read in specific rule templates. Furthermore, in some cases rule specific parameters need to be defined and relevant side files created when running specific templates.